DocumentCode
3089150
Title
A 2.8 ns 30 μW/MHz area-efficient 32-b Manchester carry-bypass adder
Author
Eriksson, Henrik ; Larsson-Edefors, Per ; Alvandpour, Atila
Author_Institution
Dept. of Phys., Linkoping Univ., Sweden
Volume
4
fYear
2001
fDate
6-9 May 2001
Firstpage
84
Abstract
A fast and area-efficient 32-b Manchester carry-bypass adder with low energy-delay product is presented in this paper. The high speed is achieved by the use of optimized bypass circuitry and fast repeater elements in the carry path. The fabricated adder has a measured worst-case delay of 2.8 ns and consumes 30 μW/MHz
Keywords
adders; carry logic; delays; repeaters; 2.8 ns; 32 bit; area-efficient Manchester carry-bypass adder; carry path; energy-delay product; optimized bypass circuitry; repeater elements; worst-case delay; Adders; Circuits; Clocks; Energy consumption; Inverters; Logic; Microprocessors; Power amplifiers; Propagation delay; Repeaters;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on
Conference_Location
Sydney, NSW
Print_ISBN
0-7803-6685-9
Type
conf
DOI
10.1109/ISCAS.2001.922175
Filename
922175
Link To Document