A high-speed CMOS incrementer/decrementer

Author

Chung-Hsun Huang ; Wang, Jinn-Shyan ; Yan-Chao Huang

Author_Institution

Inst. of Electr. Eng., Nat. Chung-Hsing Univ., Taichung, Taiwan

Volume

4

fYear

2001

fDate

6-9 May 2001

Firstpage

88

Abstract

A new circuit structure for the incrementer/decrementer is proposed in this paper. The design concept is similar to that used in our previously proposed high-speed priority encoder. This circuit is especially suitable for constructing a long incrementer/decrementer because it owns a multiple look-ahead structure and utilizes the dynamic CMOS circuit. For a 32-bit incrementer/decrementer, the proposed design can achieve a speed improvement as large as 3.0 times as compared to the adder-based design. The power-delay-product performance of the proposed design is also the best among all the incrementer/decrementers. And the new design also requires much fewer transistors than previous designs

Keywords

CMOS logic circuits; carry logic; counting circuits; frequency dividers; high-speed integrated circuits; 32 bit; dynamic CMOS circuit; high-speed CMOS; incrementer/decrementer circuit; multiple look-ahead structure; power-delay-product performance; Adders; Clocks; Counting circuits; Degradation; Digital systems; Frequency conversion; Logic circuits; Propagation delay; Silicon;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on

Conference_Location

Sydney, NSW

Print_ISBN

0-7803-6685-9

Type

conf

DOI

10.1109/ISCAS.2001.922177

Filename

922177