• DocumentCode
    3089306
  • Title

    An 800 MOPS 110 mW 1.5 V parallel DSP for mobile multimedia processing

  • Author

    Igura, H. ; Narita, S. ; Naito, Y. ; Kazama, K. ; Kuroda, I. ; Motomura, M. ; Yamashina, M.

  • Author_Institution
    NEC Corp., Japan
  • fYear
    1998
  • fDate
    5-7 Feb. 1998
  • Firstpage
    292
  • Lastpage
    293
  • Abstract
    The central signal-processing unit for a portable multimedia terminal in the coming wide-band wireless communication age should meet the following three requirements: (1) high-performance for processing video-class wide-band digital signals, (2) low-power for extended battery life, (3) programmability to cope with applications with a small chip count. Conventional DSPs lack the high-performance, while emerging media processors consume too much power. This DSP exploits task-level, coarse-grained parallelism inherent in multimedia applications. This chip achieves performance in a power-efficient manner, while maintaining the programmability of conventional DSPs.
  • Keywords
    digital signal processing chips; 1.5 V; 110 mW; central signal-processing unit; digital video; low-power circuit; mobile multimedia processing; parallel DSP; portable multimedia terminal; programmability; wideband wireless communication; CMOS technology; Clocks; Codecs; Data buses; Digital signal processing; Digital signal processing chips; Registers; Switches; Voltage; Wideband;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference, 1998. Digest of Technical Papers. 1998 IEEE International
  • Conference_Location
    San Francisco, CA, USA
  • ISSN
    0193-6530
  • Print_ISBN
    0-7803-4344-1
  • Type

    conf

  • DOI
    10.1109/ISSCC.1998.672471
  • Filename
    672471