Title :
Vertical nanowire InGaAs MOSFETs fabricated by a top-down approach
Author :
Xin Zhao ; Jianqiang Lin ; Heidelberger, Christopher ; Fitzgerald, E.A. ; del Alamo, Jesus A.
Author_Institution :
Microsyst. Technol. Labs., Massachusetts Inst. of Technol., Cambridge, MA, USA
Abstract :
Vertical In0.53Ga0.47As Gate-all around (GAA) nanowire (NW) MOSFETs fabricated by a top-down approach are demonstrated experimentally for the first time. The fabrication process features a new III-V dry etch process capable of sub-20 nm diameter NWs with an aspect ratio greater than 10. It also includes a digital etch technique to controllably reduce nanowire diameter and remove dry etch damage. With a channel length Lch=80 nm and EOT=2.2 nm, we obtain a transconductance of 730 μS/μm at 0.5 V in a 50 nm diameter NW MOSFET. The digital etch increases the transconductance by 20% and improves the subthreshold characteristics of the devices. In terms of balance of transport and short-channel effects, our MOSFETs match the best vertical nanowire devices fabricated by bottom-up techniques.
Keywords :
III-V semiconductors; MOSFET; etching; gallium arsenide; indium compounds; nanowires; GAA nanowire; III-V dry etch process; In0.53Ga0.47As; InGaAs MOSFET; NW MOSFET; digital etch technique; fabrication process; short-channel effects; size 50 nm; top-down approach; vertical gate-all around nanowire; voltage 0.5 V; Fabrication; Indium gallium arsenide; Logic gates; MOSFET; Metals; Nanoscale devices; Performance evaluation;
Conference_Titel :
Electron Devices Meeting (IEDM), 2013 IEEE International
Conference_Location :
Washington, DC
DOI :
10.1109/IEDM.2013.6724710