DocumentCode
3089375
Title
Energy efficient cache timing with performance bound
Author
Leipo, Yan ; Lam, Siew Kei ; Srikanthan, Thambipillai ; Jigang, Wu
Author_Institution
Center for High Performance Embedded Syst., Nanyang Technol. Univ., Singapore
fYear
2006
fDate
17-19 Jan. 2006
Abstract
Cache memories are the bottle-necks that limit the performance of the processors. In this paper, we present a heuristic algorithm for tuning the level-1 cache. The tuning method searches for the most energy efficient cache configuration under application performance requirement. By simulations we show that the proposed heuristic tuning algorithm is able to find the optimal or near optimal configurations. An algorithm for reducing the number of searched configurations is also proposed.
Keywords
cache storage; circuit tuning; cache memories; energy efficient cache configuration; energy efficient cache timing; heuristic tuning algorithm; level-1 cache tuning; Algorithm design and analysis; Application specific integrated circuits; Cache memory; Embedded system; Energy consumption; Energy efficiency; Heuristic algorithms; Microprocessors; System-on-a-chip; Time to market;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronic Design, Test and Applications, 2006. DELTA 2006. Third IEEE International Workshop on
Print_ISBN
0-7695-2500-8
Type
conf
DOI
10.1109/DELTA.2006.45
Filename
1581195
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