DocumentCode :
3089394
Title :
Test pattern optimization using proper in mixed-mode technique
Author :
Islam, Syed Zahidul ; Ali, Mohd Alauddin Mohd
Author_Institution :
Sch. of Eng., Swinburne Univ. of Technol., Sarawak, Malaysia
fYear :
2006
fDate :
17-19 Jan. 2006
Abstract :
This paper presents a test pattern optimization approach using a proper number of seed selection in mixed-mode patterns. In mixed-mode patterns, the test set is assembled from LFSR based pseudorandom and deterministic patterns. The efficiency of this approach is largely determined by the ratio of those test patterns in the final test. The experiment results show that the total number of patterns in this optimized mixed-mode is minimized compared to conventional mixed-mode technique.
Keywords :
automatic test pattern generation; digital integrated circuits; integrated circuit testing; shift registers; LFSR deterministic pattern; LFSR pseudorandom pattern; linear feedback shift register; mixed-mode patterns; seed selection; test pattern optimization; Assembly; Circuit faults; Circuit testing; Cost function; Digital systems; Hardware; Integrated circuit testing; Linear feedback shift registers; System testing; Test pattern generators;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electronic Design, Test and Applications, 2006. DELTA 2006. Third IEEE International Workshop on
Print_ISBN :
0-7695-2500-8
Type :
conf
DOI :
10.1109/DELTA.2006.86
Filename :
1581197
Link To Document :
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