Compensation-Capacitor Free Pseudo Three-Stage Amplifier with Large Capacitive Loads

A pseudo three-stage amplifier with large capacitive loads is proposed in this paper. The proposed idea enables pole-relocation such that a single-pole amplifier can be virtually developed. The pole-relocation is done by using the flipped voltage follower to insolate the large parasitic capacitance and the large drain resistance of MOSFET devices. The idea was simulated using the BSIM models of a commercial 0.35-mum CMOS technology. No on-chip capacitor is needed to achieve the stability of the amplifier. The unity-gain frequency of the amplifier based on the proposed technique is 7.3 MHz and the phase margin is 59deg when driving a 500-pF load. When comparing to the Miller-compensated counterpart, the bandwidth improvement is about 52 times. A comparison based on the well-accepted figure of merits (12170, based on the power consumption, and 25420, based on the supply current) is shown.