Interface engineering for thermal disturb immune phase change memory technology

The Phase Change Memory (PCM) technology has followed the scaling roadmap [1] from the 180nm down to the 45nm technology node [2-4], in the last one going in volume production. In a PCM array, thermal crosstalk is referred to as a potential concern due to a temperature raise driven by the programming operation in a cell and its impact on data retention in the neighbor ones. In fact a programming operation in PCM induces a temperature raise in the cell surrounding environment [1]. Such issue has been already addressed in 54nm PCM [5] through an accurate tuning of the programming algorithm. Although effective, such an approach implies several constraints for further optimization of the PCM array performances. In this work we empirically investigate the thermal crosstalk in 45nm PCM arrays, clearly highlighting the key role of the interface thermal resistances engineering. PCM cell design rules for thermal crosstalk immune operation are discussed and implemented on silicon, leading to a fully disturb-immune qualified process.