Leakage power estimation and minimization in VLSI circuits

In low-power design for circuits, people want to reduce the power supply voltage, and this requires the transistor threshold voltages to also be reduced to maintain throughput and noise margins. However. This increases the subthreshold leakage current in p and n MOSFETs, which begins to increase the overall power in large circuits. Because the leakage power in CMOS gates has state dependent status, we solve this problem by choosing one specific state (the best state) with minimum leakage power in all input combinations. This implies that we can apply the best state for this CMOS gate when it is not activated (in idle mode). This helps to reduce leakage power dissipation in a large system. This paper shows how a linear programming model and a heuristic algorithm can be used to obtain we optimal solution in determining the best state with minimum leakage energy for CMOS gates such as Inverter, AND, OR, NAND, and NOR gates. The accurate close form model that is modified and used for estimation of the leakage power for CMOS gate