Title :
A new logic synthesis and optimization procedure
Author :
Cheng, Kuo-Hsiizg ; Hsieh, Ven-Chieh
Author_Institution :
Dept. of Electr. Eng., Tamkang Univ., Tamsui, Taiwan
Abstract :
The objective of this work is to develop a new logic circuit synthesis and optimization procedure for arbitrary logic function. Following the procedure, we may get a new high performance logic circuit family, which has low power consumption, low power-delay product, area efficiency and suitable for low supply voltage. The new logic family based upon the proposed design procedures has certain advantage over CMOS, DVL and DPL in most cases
Keywords :
circuit optimisation; logic design; low-power electronics; area efficiency; logic circuit synthesis; low-power low-voltage design; optimization; power consumption; power-delay product; CMOS logic circuits; CMOS technology; Circuit synthesis; Energy consumption; Logic circuits; Logic design; Logic functions; Low voltage; MOSFETs; Page description languages;
Conference_Titel :
Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on
Conference_Location :
Sydney, NSW
Print_ISBN :
0-7803-6685-9
DOI :
10.1109/ISCAS.2001.922202
