Title :
A 2.7 ns 0.25 /spl mu/m CMOS 54/spl times/54 b multiplier
Author :
Hagihara, Y. ; Inui, S. ; Yoshikawa, A. ; Nakazato, S. ; Iriki, S. ; Ikeda, R. ; Shibue, Y. ; Inaba, T. ; Kagamihara, M. ; Yamashina, M.
Author_Institution :
NEC Corp., Tokyo, Japan
Abstract :
A 0.25 /spl mu/m CMOS 2.7 ns latency multiplier capable of supporting a 400 MHz double-stage pipelined FPU consists of Booth recoders, partial product generators, a 4-to-2 compressor tree, and a 108 b final adder. The 4-to-2 compressor combines dual-rail domino and pass-transistor logic gates. The compressor consists of two carry-save adders (CSAs = full adders), and each of the CSAs includes two domino gates for generating carries and a pass-transistor logic gate for generating sums. The critical path in a 4-to-2 compressor tree has conventionally been its carry path. By designing the carry path, however, with domino gates, it has improved the critical delay time so that a 5-input XOR sum path becomes the critical path. Dual-rail pass-transistor logic is used to improve XOR speed, enabling a simple selector to be an XOR gate. The resulting speed is greater than that of a single-rail XOR gate.
Keywords :
CMOS logic circuits; 0.25 micron; 2.7 ns; 4-to-2 compressor tree; 400 MHz; 5-input XOR sum path; 54 bit; Booth recoders; CMOS 54/spl times/54 b multiplier; carry-save adders; critical delay time; double-stage pipelined FPU; dual-rail domino logic gates; floating point unit; partial product generators; pass-transistor logic gates; Adders; CMOS technology; Circuit simulation; Clocks; Delay effects; Paper technology; Solid modeling; Solid state circuits; Voltage;
Conference_Titel :
Solid-State Circuits Conference, 1998. Digest of Technical Papers. 1998 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-4344-1
DOI :
10.1109/ISSCC.1998.672473
