A 2.7 ns 0.25 /spl mu/m CMOS 54/spl times/54 b multiplier

A 0.25 /spl mu/m CMOS 2.7 ns latency multiplier capable of supporting a 400 MHz double-stage pipelined FPU consists of Booth recoders, partial product generators, a 4-to-2 compressor tree, and a 108 b final adder. The 4-to-2 compressor combines dual-rail domino and pass-transistor logic gates. The compressor consists of two carry-save adders (CSAs = full adders), and each of the CSAs includes two domino gates for generating carries and a pass-transistor logic gate for generating sums. The critical path in a 4-to-2 compressor tree has conventionally been its carry path. By designing the carry path, however, with domino gates, it has improved the critical delay time so that a 5-input XOR sum path becomes the critical path. Dual-rail pass-transistor logic is used to improve XOR speed, enabling a simple selector to be an XOR gate. The resulting speed is greater than that of a single-rail XOR gate.