A High Speed CMOS Transmitter and Rail-to-Rail Receiver

Author

Zhang, Feng ; Yang, Zongren ; Feng, Wei ; Cui, Hao ; Huang, Lingyi ; Hu, Weiwu

Author_Institution

Inst. of Comput. Technol., Beijing

fYear

2008

fDate

23-25 Jan. 2008

Firstpage

67

Lastpage

70

Abstract

This paper presents a high speed low voltage differential signal (LVDS) interface circuit for CPU, LCD, FPGA and other fast links. In the proposed transmitter a stable reference and a common mode feedback circuit are applied into the LVDS drivers, which enable the transmitter to tolerate the variations of process, temperature and supply voltage. The proposed receiver implements a rail-to-rail amplifier architecture which allows a 1.6 Gb/s transmission. The transmitter and receiver are implemented in HJ TC 3.3 v, 0.18 plusmn CMOS technology. Transmission operations up to 1.6 Gb/s with random data patterns were demonstrated. The transmitter and receiver pad cells exhibit a power consumption of 35 mW and 6 mW respectively.

Keywords

CMOS integrated circuits; amplifiers; circuit feedback; driver circuits; radio receivers; radio transmitters; CMOS technology; CPU; FPGA; LCD; LVDS drivers; LVDS interface circuit; bit rate 1.6 Gbit/s; common mode feedback circuit; high speed CMOS transmitter; low voltage differential signal interface circuit; power 35 mW; power 6 mW; rail-to-rail amplifier architecture; rail-to-rail receiver; voltage 3.3 V; Application software; CMOS technology; Circuit testing; Driver circuits; Electronic equipment testing; Feedback circuits; Low voltage; Optical transmitters; Signal design; Temperature; LVDS rail-to-rail;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronic Design, Test and Applications, 2008. DELTA 2008. 4th IEEE International Symposium on

Conference_Location

Hong Kong

Print_ISBN

978-0-7695-3110-6

Type

conf

DOI

10.1109/DELTA.2008.32

Filename

4459511