DocumentCode
3089944
Title
A low-power high-speed 1-Mb CMOS SRAM
Author
Soon-Hwei, Tan ; Poh-Yee, Loh ; Sulaiman, Mohd-Shahiman
Author_Institution
Fac. of Eng., Multimedia Univ., Selangor, Malaysia
fYear
2006
fDate
17-19 Jan. 2006
Abstract
An asynchronous dual-port 1-Mb CMOS SRAM is described. The SRAM can operate at a maximum frequency of 220MHz in dual-port mode and dissipates a minimum active power of 31mW and consumes a minimum standby power of 80nW. Simulation results show that the circuit functions properly over a wide range of process, voltage & temperature (PVT) corners. SRAM was custom designed using TSMC CMOS 0.25μm 1P5M salicide process and occupies a silicon area of approximately 115mm2 (11.5mm × 10mm).
Keywords
CMOS memory circuits; SRAM chips; circuit simulation; high-speed integrated circuits; low-power electronics; silicon; 0.25 micron; 1 MByte; 1P5M salicide process; 220 MHz; 31 mW; 80 nW; asynchronous CMOS SRAM; high-speed CMOS SRAM; low-power CMOS SRAM; Batteries; Circuit simulation; Circuit synthesis; Decoding; Delay; Frequency; Power dissipation; Power engineering and energy; Random access memory; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronic Design, Test and Applications, 2006. DELTA 2006. Third IEEE International Workshop on
Print_ISBN
0-7695-2500-8
Type
conf
DOI
10.1109/DELTA.2006.6
Filename
1581226
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