An Efficient Design of Single Event Transients Tolerance for Logic Circuits

In the presence of radiation, particle strikes can cause temporary signal errors in integrated circuits (ICs). Particle strikes that directly affect memory are known as single event upsets (SEUs), while strikes that affect combinational logic are called single event transients (SETs). SETs are becoming more of an issue as technology improves, as the properties that masked these faults in the past are decreasing in influence. This paper presents circuit design techniques to remove the effects of such SET pulses from the circuit. An optimized design is developed, and its performance of area and SET immunity is superior to other design methods for SET mitigation. Simulation results show that its SET immunity is more effective than the technique using Guard-gate-based structure, and its area penalty is less than the method using cascade-voltage switch logic gates based structure.