Title :
Proceedings 17th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems. DFT 2002
Keywords :
VLSI; circuit simulation; design for testability; error detection; fault tolerance; integrated circuit testing; integrated circuit yield; low-power electronics; redundancy; sequential circuits; system-on-chip; VLSI systems; concurrent error detection; defect analysis; defect tolerance; error correcting codes; fault injection; fault tolerance; low-power techniques; redundancy; repair; sequential circuit design; simulation techniques; system-on-chip; test generation; testability; yield prediction;
Conference_Titel :
Defect and Fault Tolerance in VLSI Systems, 2002. DFT 2002. Proceedings. 17th IEEE International Symposium on
Conference_Location :
Vancouver, BC, Canada
Print_ISBN :
0-7695-1831-1
DOI :
10.1109/DFTVS.2002.1173495
