Title :
Manufacturability analysis of analog CMOS ICs through examination of multiple layout solutions
Author :
Khademsameni, Pedram ; Syrzycki, Marek
Author_Institution :
Sch. of Eng. Sci., Simon Fraser Univ., Burnaby, BC, Canada
Abstract :
Introduces a methodology for the manufacturability analysis of analog CMOS ICs. The methodology is based on examination of several layout solutions of a single circuit. A critical area approach to evaluate a theoretical random-defect limited yield is applied for each layout solution. Users can choose the appropriate layout solution after comparing the theoretical yield values and considering results obtained from economical post-layout simulation tools. The theoretical yield has been proposed as one of possible quality factors in the design for manufacturability. The multi-layout approach, which is presented here, has been implemented in a CAD tool (ALDAC). The use of this CAD tool for layout generation and analysis of circuit manufacturability will be presented here.
Keywords :
CMOS analogue integrated circuits; Q-factor; circuit layout CAD; circuit simulation; design for manufacture; integrated circuit layout; integrated circuit yield; ALDAC; CAD tool; analog CMOS ICs; critical area approach; design for manufacturability; layout solutions; manufacturability analysis; multi-layout approach; multiple layout solutions; post-layout simulation tools; quality factors; random-defect limited yield; Analog integrated circuits; CMOS analog integrated circuits; CMOS process; Circuit simulation; Fabrication; Integrated circuit layout; Integrated circuit modeling; Manufacturing processes; Pulp manufacturing; Q factor;
Conference_Titel :
Defect and Fault Tolerance in VLSI Systems, 2002. DFT 2002. Proceedings. 17th IEEE International Symposium on
Print_ISBN :
0-7695-1831-1
DOI :
10.1109/DFTVS.2002.1173496
