Predictive Die-Level Reliability-Yield Modeling for Deep Sub-micron Devices

An increasing number of integrated circuits are going into the automotive sector where requirements on dependability are very high. As a result, there is a strong push in the semiconductor industry for achieving higher reliability standards while maintaining (or even lowering) the associated cost. Lately two efficient approaches to increase the effectiveness of reliability testing (including burn-in) have emerged. The first involves additional reliability test insertions. It is quite effective but limited to specific technology and processes. A more robust approach is to screen out devices with latent defects at probe (wafer level) through appropriate selection criteria before devices reach burn-in at the package- level. Traditional six-sigma quality assurance procedures are inadequate in coping with the fabrication process variations because the process is not static. Dynamic parts average testing (PAT) has been introduced by the Automotive Electronics Council to identify abnormal parts from a large population mean. It is the first standard procedure that deviates from the traditional six-sigma approach. Independent studies by Intel and IBM have shown that a die-level reliability predictor can screen unreliable devices better than dynamic PAT (which is based on a lot-level methodology). However, the die-level predictive model is relatively new and thus it needs further investigation to prove its usability in different technology and process settings. This paper studies the die-level predictive model for a specific wafer fabrication technology and critically assesses its performance and feasibility for implementation in a real-world production testing.