FPGA Based Real Time Solution for Sensitivity Time Control

This work mainly focuses on the digitisation of Sensitivity Time Control for Radar receivers using Field Programmable Gate Arrays (FPGAs). Sensitivity Time Control (STC) is one of the gain control methods for RADAR signal processing. Gain control is used to adjust the sensitivity of the receiver thereby regulating the intensity of the returns. STC helps in increasing the dynamic range of the receiver and thus prevents the receiver saturation. STC is achieved by applying an attenuation that varies with the range thus making the receiver signal strength range independent. The attenuation to be applied to the echo signal is constant up to a certain range and then varies exponentially depending upon the clutter environment. The digital implementation technique using FPGAs gives a high degree of flexibility in selecting the STC laws in real time depending upon the environment. This design calculates the attenuation value up to an accuracy of 0.001dB.