A 4.25 Gb/s CMOS fiber channel transceiver with asynchronous binary tree-type demultiplexer and frequency conversion architecture

Author

Fukaishi, M. ; Nakamura, K. ; Sato, M. ; Tsulsui, Y. ; Kishi, S. ; Yotsuyanagi, M.

Author_Institution

NEC Corp., Kanagawa, Japan

fYear

1998

fDate

5-7 Feb. 1998

Firstpage

306

Lastpage

307

Abstract

A single-chip 4.25 Gb/s 32:1, 1:32 transceiver, meeting the emerging ANSI fiber channel (FC) standard, uses 0.25 /spl mu/m CMOS technology. To achieve 4.25 Gb/s operation, the features include: 1) an asynchronous tree-type 1:8 demultiplexer (DEMUX), 2) an 8 b to 10 b parallel-to-parallel frequency converter, and 3) comma-detection and word-alignment logic. The transceiver consumes 600 mW in 4.25 Gb/s operation with a 2.5 V supply. Higher-speed operation that that of a previous CMOS FC design is achieved.

Keywords

CMOS digital integrated circuits; 0.25 micron; 2.5 V; 4.25 Gbit/s; 600 mW; ANSI fiber channel standard; CMOS fiber channel transceiver; asynchronous demultiplexer; binary tree-type demultiplexer; comma-detection logic; frequency conversion architecture; parallel-to-parallel frequency converter; single-chip transceiver; word-alignment logic; Clocks; Frequency conversion; Registers; Solid state circuits; Timing; Transceivers; Transmitters; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 1998. Digest of Technical Papers. 1998 IEEE International

Conference_Location

San Francisco, CA, USA

ISSN

0193-6530

Print_ISBN

0-7803-4344-1

Type

conf

DOI

10.1109/ISSCC.1998.672477

Filename

672477