Title :
Design of High-Speed Floating Point Multiplier
Author :
Siddamal, Saroja V. ; Banakar, R.M. ; Jinaga, B.C.
Author_Institution :
B.V.B C.E.T, Hubli
Abstract :
Floating-point (FP) multiplication finds application in image and signal processing. This paper presents a hardware implementation of optimized IEEE 754 single precision floating-point multiplier. The design is simulated using Modelsim and synthesized using Virtix E Xilinx ISE. An improvement of 57.77% in area and 44.52% in delay is shown.
Keywords :
floating point arithmetic; logic design; multiplying circuits; Modelsim; Virtix E Xilinx ISE; floating point arithmetic; hardware implementation; high-speed floating point multiplier; multiplying circuits; Adders; Delay; Digital filters; Digital signal processing; Digital signal processors; Electronic equipment testing; Hardware; Signal processing; Signal processing algorithms; Signal synthesis; Booth algorithm.; CSD algorithm; FP operations; Fast Carry look ahead adder (MCLA);
Conference_Titel :
Electronic Design, Test and Applications, 2008. DELTA 2008. 4th IEEE International Symposium on
Conference_Location :
Hong Kong
Print_ISBN :
978-0-7695-3110-6
DOI :
10.1109/DELTA.2008.19
