Self-checking and fault tolerance quality assessment using fault sampling

The computational effort associated with fault simulation (FS) processes in digital systems can become overwhelming, due to circuit complexity, test pattern size or fault list size. The same applies when safety properties (such as fault tolerance or fail-safe) need to be verified in a new product development, in the design environment. If a bridging fault model replaces the simple stuck-at fault model, the fault list size easily becomes very large. If the product needs to comply to safety standards, such as EN298, these properties need to be verified in the presence of double faults, which explodes the fault list dimension. In this paper, a novel method is proposed to deal with this problem, based on fault sampling. A model to compute the confidence level that the global fault coverage, FC, is within the interval [FC_min 100%] is proposed. A case study, an ASIC for a safety-critical gas burner control system, is used to ascertain the usefulness of the proposed methodology.