DocumentCode
3090778
Title
Using an Analytical Model of Shared Caches for Selecting the Optimal Parallelization Scheme
Author
Andrade, Diego ; Fraguela, Basilio B. ; Doallo, Ramón
Author_Institution
Comput. Archit. Group, Univ. da Coruna, A Coruna, Spain
fYear
2012
fDate
10-13 July 2012
Firstpage
588
Lastpage
594
Abstract
Multicores are now the norm. Their cache hierarchy has often a last level shared cache. The performance of this shared cache during the execution of multithreaded applications depends on the parallelization scheme followed. For example, critical parameters for the performance of parallelized loops are the number of threads and the block size. The selection of the optimal scheme in a compiler can be guided using heuristics or the execution time. Heuristics can be imprecise, while an execution time guided search is very time-consuming. This paper shows the usage of an analytical model to predict the cache behavior of shared caches during the execution of multithreaded applications that have been parallelized at loop level. The model predicts the number of misses generated by a given code when different number of threads or block sizes are used. The execution time of the codes analyzed is highly correlated to the number of misses generated in the shared cache, thus, the prediction of the model is a powerful tool to select the best parallelization scheme for them.
Keywords
cache storage; multi-threading; multiprocessing systems; program compilers; storage management; analytical model; cache hierarchy; compiler; execution time guided search; heuristics; last level shared cache; multicores; multithreaded application; optimal parallelization scheme; optimal scheme; parallelized loops; Analytical models; Data structures; Dynamic scheduling; Instruction sets; Mathematical model; Multicore processing; Predictive models; analytical modeling; cache memories; parallel applications; shared cache;
fLanguage
English
Publisher
ieee
Conference_Titel
Parallel and Distributed Processing with Applications (ISPA), 2012 IEEE 10th International Symposium on
Conference_Location
Leganes
Print_ISBN
978-1-4673-1631-6
Type
conf
DOI
10.1109/ISPA.2012.88
Filename
6280348
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