Emulation-based design errors identification

Design verification has a large impact on the final testability of a system. The identification and removal of design errors from the initial design steps increases the testing quality of the entire design flow. We propose in this paper to exploit the potentialities of an emulator to accelerate a validation methodology for RTL designs. Alternative emulator configurations are compared in order to evaluate the performance speed-up of the presented methodology. The RTL design functionalities are compared with a System C executable specification model.