A Prevenient Voltage Stress Test Method for High Density Memory

The most effective acceleration factor of reliability is the high voltage stress. However high electric field generated on thin gate oxide transistors in nanometer technology becomes the uppermost limit. In this paper, an improved voltage stress method for DRAM with the 6F2 structure and the open bit line scheme is proposed to enhance the Early Life Failure Rates (ELFR) and the yield of package test. The proposed method reduces the degradation of transistors caused by a high voltage stress. Experimental results show that the proposed method improves the yield of package test and the characteristic of refresh, and avoids the degradation of transistors using voltage ramp stress (VRS).