An infrastructure for the dissemination of information on KGD

At the present time there are various silicon foundries and chip houses both in Europe and the US who have an approach to KGD. This may be in the form of supplying various grades of goodness depending on the application and cost/yield break points. Such KGD from various sources therefore can be supplied DC probed; burnt-in as bare die and hot tested etc. However this facility is only available from a limited number of sources at present. The main activity is, therefore, in the design and generation of a database for the selection of KGD and other bare die for the design of MCMs and hybrid circuits. Once selection is made the bare die footprints and simulation models will be able to be downloaded to CAD MCM design workstations for the actual layout of the modules. Also thermal and electrical simulations will be able to be carried out at this stage. The database will contain all assembly technologies of die if they are available. These include wire bond, TAB, flip chip and CSP (chip size package)