DocumentCode :
3091981
Title :
Compile time data transfer analysis
Author :
Zhang, Wendy ; Leiss, Ernst L.
Author_Institution :
Dept. of Comput. Inf. Syst., Southern Univ., New Orleans, LA, USA
fYear :
2002
fDate :
23-25 Oct. 2002
Firstpage :
222
Lastpage :
225
Abstract :
The design and implementation of compilers for high performance compiler systems require a thorough understanding of the target architecture to deliver the highest level of performance. It is important to know the I/O behavior on memory hierarchies. The compile time data transfer analysis computes an accurate approximation on the number of data transfers between main and secondary memory when the least recently used replacement policy is applied. This analysis is performed at compile time; since some details are unknown, simplifying assumptions have to be accepted from the outset. The analyzer estimates in reasonable precision the number of page transfers that a program needs for execution, based on the parameters of the system available at compile time. The results reflect the real behavior of the system when executing the program and can therefore be used to compare situations derived for the same program after code restructuring.
Keywords :
electronic data interchange; program compilers; compiler; input output behavior; least recently used replacement policy; page reference sequence; page transfers; time data transfer; Algorithm design and analysis; Concurrent computing; Data analysis; Electronic mail; High performance computing; Information analysis; Information systems; Memory management; Performance analysis; Runtime library;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Algorithms and Architectures for Parallel Processing, 2002. Proceedings. Fifth International Conference on
Conference_Location :
Beijing, China
Print_ISBN :
0-7695-1512-6
Type :
conf
DOI :
10.1109/ICAPP.2002.1173577
Filename :
1173577
Link To Document :
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