A CMOS triple-band fractional-N frequency synthesizer for GSM/GPRS/EDGE applications

Author

Ping Wu ; He, Kai

Author_Institution

Mobilink Telecom Inc., Santa Clara, CA, USA

Volume

4

fYear

2001

fDate

6-9 May 2001

Firstpage

706

Abstract

A low-cost low-power fractional-N synthesizer IC targeting GSM (900 MHz), DCS (1800 MHz) and PCS (1900 Hz) tri-band cellular phone applications has been implemented. It integrates prescalers, dividers, phase/frequency detectors, charge pumps of both RF and IF PLLs, and all necessary baseband interface control. Its RF section features a fractional-N synthesizer with digital 3^rd-order delta-sigma noise shaping. Block-wise power management scheme is used to achieve standby current <1 μA at 2.5 V power supply. The core of the synthesizer occupies 1.8 mm×0.8 mm silicon in a 0.25 μm triple-metal CMOS process. Functionality was verified for frequencies up to 2 GHz. The architecture, circuit design and simulation of the synthesizer are presented in this paper

Keywords

CMOS integrated circuits; UHF integrated circuits; cellular radio; frequency synthesizers; low-power electronics; 0.25 micron; 1800 MHz; 1900 MHz; 2.5 V; 900 MHz; CMOS IC; EDGE; GPRS; GSM; IF PLL; RF PLL; baseband interface control; charge pump; digital third-order delta-sigma noise shaping; divider; frequency detector; low-power fractional-N frequency synthesizer; phase detector; power management; prescaler; triple-band cellular phone; Application specific integrated circuits; Cellular phones; Distributed control; Frequency conversion; Frequency synthesizers; GSM; Integrated circuit synthesis; Personal communication networks; Phase detection; Radio frequency;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on

Conference_Location

Sydney, NSW

Print_ISBN

0-7803-6685-9

Type

conf

DOI

10.1109/ISCAS.2001.922335

Filename

922335