Design-for-ESD-reliability for high-frequency I/O interface circuits in deep-submicron CMOS technology

Author

Lee, Jnesik ; Huh, Yooizjoizg ; Bendix, P. ; Sung-Mo Steve Kang

Author_Institution

Illinois Univ., Urbana, IL, USA

Volume

4

fYear

2001

fDate

6-9 May 2001

Firstpage

746

Abstract

This paper reports the effect of electrostatic discharge (ESD) induced impedance mismatch on the performance degradation in high speed I/O interfaces. The impedance mismatch after ESD stressing is explained by on-chip termination resistance distortion. From the circuit-level ESD simulation and experimental results. ESD induced termination resistance degradation should be taken into consideration in the design of the high speed I/O circuits. Proposed design optimization methods of on-chip termination resistors provide sufficient safeguard against ESD damage and improve I/O signal integrity

Keywords

CMOS integrated circuits; VLSI; circuit optimisation; design for manufacture; electrostatic discharge; high-speed integrated circuits; integrated circuit design; integrated circuit reliability; I/O signal integrity; deep-submicron CMOS technology; design optimization methods; design-for-ESD-reliability; electrostatic discharge; high-frequency I/O interface circuits; impedance mismatch; on-chip termination resistance distortion; on-chip termination resistors; performance degradation; CMOS technology; Circuits; Electrostatic discharge; Impedance; Large scale integration; Nonlinear distortion; Resistors; Termination of employment; Thermal degradation; Thermal stresses;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on

Conference_Location

Sydney, NSW

Print_ISBN

0-7803-6685-9

Type

conf

DOI

10.1109/ISCAS.2001.922345

Filename

922345