Design-for-ESD-reliability for high-frequency I/O interface circuits in deep-submicron CMOS technology

This paper reports the effect of electrostatic discharge (ESD) induced impedance mismatch on the performance degradation in high speed I/O interfaces. The impedance mismatch after ESD stressing is explained by on-chip termination resistance distortion. From the circuit-level ESD simulation and experimental results. ESD induced termination resistance degradation should be taken into consideration in the design of the high speed I/O circuits. Proposed design optimization methods of on-chip termination resistors provide sufficient safeguard against ESD damage and improve I/O signal integrity