Multiway partitioner for high performance FPGA based board architectures

Field-programmable gate array based board architectures are becoming fairly common for rapid prototyping and custom computing. In order to map large designs on multiple FPGA based boards, the design has to be partitioned into two or more segments. In this paper we describe the architecture, constraints, and a solution to the area and pin constrained partitioning problem. Our effort is directed towards partitioning “huge” designs in relatively small amount of time, thus giving the designer a capability to explore many mapping solutions. The board level architecture is based on multi-chip modules, where each MCM consists of three Xilinz 4025 FPGAs and a dual ported one mega byte SRAM. In its smallest configuration the board can map 300,000 gate size designs