An Efficient PCS to Transmit FEC-coded Frames in Ethernet PON

Author

Yen, Chih-Hsu

Author_Institution

Ind. Technol. Res. Inst., Hsinchu

fYear

2008

fDate

18-20 Nov. 2008

Firstpage

245

Lastpage

250

Abstract

A method to efficiently transmit FEC-coded frames in PCS for Ethernet PON is proposed. Comparing with IEEE 802.3ah Clause 65.2.3, the proposed architecture requires only one 8b/10b encoder and is IEEE 802.3ah-compliant. This method speeds up the circuit and reduces the gate counts. In StratixII EP2S180 FPGA, the proposed method, comparing with the standard, saves 40.7% ALUs and increases 18% speed. Using TSMC013LP technology, our method saves 29% gate counts, and increases 26% speed. Additionally, the proposed method can be easily concatenated after the ordinary Ethernet TRANSMIT process with the removal of the 8b/10b encoder.

Keywords

field programmable gate arrays; forward error correction; optical fibre LAN; Ethernet frame; Ethernet passive optical network; IEEE 802.3ah Clause 65.2.3; PCS; field programmable gate arrays; forward error correction; gate counts; physical coding sublayer; Concatenated codes; Decoding; EPON; Encoding; Ethernet networks; Field programmable gate arrays; Forward error correction; Optical fiber networks; Passive optical networks; Personal communication networks; EPON; Ethernet frame; FEC transmission; PCS; line code;

fLanguage

English

Publisher

ieee

Conference_Titel

High Capacity Optical Networks and Enabling Technologies, 2008. HONET 2008. International Symposium on

Conference_Location

Penang

Print_ISBN

978-1-4244-2960-8

Electronic_ISBN

978-1-4244-2961-5

Type

conf

DOI

10.1109/HONET.2008.4810243

Filename

4810243