A 27–34 GHz CMOS medium power amplifier with a flat power performance

Author

Chao-Hsiuan Tsay ; Jui-Chih Kao ; Kun-Yao Kao ; Kun-You Lin

Author_Institution

Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan

fYear

2012

fDate

4-7 Dec. 2012

Firstpage

1

Lastpage

3

Abstract

This paper presents a 27-34 GHz medium power amplifier in 65-nm CMOS technology. The amplifier is designed to amplify the LO signals from the 30-GHz VCO in a 60-GHz sub-harmonic direct-conversion system. The proposed amplifier achieves a measured gain of higher than 22.8 dB from 27 to 34 GHz, and the gain deviation is within 1 dB. The measured results show a PAE up to 13% at 1-dB compression power (P_1dB), and a 7.7-dBm P_1dB at 30 GHz. The peak PAE and the saturation power (P_sat) are 23.3% and 10.6 dBm at 30 GHz, respectively. The P_1dB is between 6.8 and 7.7 dBm while the P_sat is between 9.7 and 10.8 dBm from 27 to 34 GHz. The chip size is 0.36 mm² including all testing pads.

Keywords

CMOS analogue integrated circuits; power amplifiers; voltage-controlled oscillators; CMOS medium power amplifier; CMOS technology; LO signal; PAE; VCO; amplifier design; flat power performance; frequency 27 GHz to 34 GHz; frequency 60 GHz; saturation power; size 65 nm; subharmonic direct-conversion system; CMOS integrated circuits; CMOS technology; Gain; Gain measurement; Impedance matching; Power amplifiers; Semiconductor device measurement; CMOS; Ka band; MMIC; broadband; power amplifier;

fLanguage

English

Publisher

ieee

Conference_Titel

Microwave Conference Proceedings (APMC), 2012 Asia-Pacific

Conference_Location

Kaohsiung

Print_ISBN

978-1-4577-1330-9

Electronic_ISBN

978-1-4577-1331-6

Type

conf

DOI

10.1109/APMC.2012.6421478

Filename

6421478