DocumentCode
3092697
Title
Efficient compile-time analysis of cache behaviour for programs with IF statements
Author
Vera, Xavier ; Xue, Jingling
Author_Institution
Institutionen for Datateknik, Vasteras, Sweden
fYear
2002
fDate
23-25 Oct. 2002
Firstpage
396
Lastpage
407
Abstract
This paper presents an analytical method for analysing efficiently the cache behaviour of Perfect loop nests containing IF statements with compile-time-analysable conditionals. We discuss the derivations of reuse vectors in the presence of IF statements, present miss equations for characterising the cache behaviour of a program and give algorithms for solving these equations for cache misses. We show that our method, together with loop sinking, can be used to analyse a large number of imperfect loop nests that cannot be analysed previously-17% more loop nests than previously in SPECfp95, Perfect Suite, Livermore kernels, Linpack and Lapack. Validation against cache simulation demonstrates the efficiency and accuracy of our method. Our method can be used to guide compiler cache optimisations and improve the performance of cache simulators and profilers.
Keywords
cache storage; parallel programming; program control structures; IF statements; cache behaviour; compile-time analysis; data caches; loop sinking; perfect loop nests; Bismuth; Parallel processing;
fLanguage
English
Publisher
ieee
Conference_Titel
Algorithms and Architectures for Parallel Processing, 2002. Proceedings. Fifth International Conference on
Conference_Location
Beijing, China
Print_ISBN
0-7695-1512-6
Type
conf
DOI
10.1109/ICAPP.2002.1173608
Filename
1173608
Link To Document