A 60GHz power amplifier using high common-mode rejection technique

Author

Minami, Ryutaro ; Bunsen, K. ; Okada, Kenichi ; Matsuzawa, Akira

Author_Institution

Dept. of Phys. Electron., Tokyo Inst. of Technol., Tokyo, Japan

fYear

2012

fDate

4-7 Dec. 2012

Firstpage

10

Lastpage

12

Abstract

This paper proposes the method of realization of high common-mode rejection ratio(CMRR) at 60 GHz. High CMRR can compensate the differential mismatch. In the proposed method, virtual ground for differential-mode and LC peaking for common-mode are utilized. To confirm the effect of this technique, the 2-stage differential power amplifier is fabricated in a 65nm CMOS process. It achieves a CMRR of 26 dB, a power gain of 12.1 dB, a peak PAE of 11.1%, a P_sat of 9.0 dBm, a power consumption of 45.8mW from a 1.0V power supply.

Keywords

CMOS integrated circuits; power amplifiers; CMOS process; CMRR; LC peaking; common mode; differential mismatch; differential mode; frequency 60 GHz; gain 12.1 dB; high common-mode rejection ratio; power 45.8 mW; power amplifier; size 65 nm; virtual ground; voltage 1 V; CMOS integrated circuits; CMOS process; Capacitance; Gain; Impedance; Power transmission lines; Radio frequency; 60GHz; CMOS; CMRR; Power amplifiers;

fLanguage

English

Publisher

ieee

Conference_Titel

Microwave Conference Proceedings (APMC), 2012 Asia-Pacific

Conference_Location

Kaohsiung

Print_ISBN

978-1-4577-1330-9

Electronic_ISBN

978-1-4577-1331-6

Type

conf

DOI

10.1109/APMC.2012.6421481

Filename

6421481