A hardware/software codesign partitioner for ASIP design

Author

Alomary, Alauddin Yousif

Author_Institution

Appl. Sci. Univ., Amman, Jordan

Volume

1

fYear

1996

fDate

13-16 Oct 1996

Firstpage

251

Abstract

This paper introduces a new codesign partitioning method used in automating the design of ASIP (Application Specific Integrated Processor). The codesign partitioning problem is formalized as a combinatorial optimization problem that partitions the operations into hardware and software such that a certain performance goal is met using minimum hardware resources. A branch-and-bound algorithm is used to solve the presented formalization. The proposed method is found to be effective in producing a quality design in reasonable time with a minimum of design interaction

Keywords

application specific integrated circuits; circuit CAD; computer aided software engineering; logic CAD; microprocessor chips; optimisation; ASIP design; CAD; application specific integrated processor; branch/bound algorithm; codesign partitioning method; combinatorial optimization problem; hardware/software codesign partitioner; Application software; Application specific processors; Arithmetic; Computer architecture; Energy consumption; Hardware; Optimization methods; Partitioning algorithms; Process design; Software performance;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Circuits, and Systems, 1996. ICECS '96., Proceedings of the Third IEEE International Conference on

Conference_Location

Rodos

Print_ISBN

0-7803-3650-X

Type

conf

DOI

10.1109/ICECS.1996.582790

Filename

582790