An inductorless peaking technique applied to MOS current-mode logic gates

A novel inductorless peaking technique is demonstrated to improve the time-domain response of MOS current mode logic (MCML) gates. The proposed circuit design occupies signi-cantly less area compared to passive inductive peaking solutions, and achieves a speed increase of up to 17% in detailed post-layout simulations, and up to 8.5% in experimental validation. Sample circuits designed using a standard 0.18 μm CMOS technology with 1.8 V power supply exhibit propagation delay times of about 35ps, which allows reliable circuit operation at GHz range clock frequency. The circuit technique discussed here is suitable for cell-bared high-density logic designs.