A general piece-wise nonlinear library modeling format and size reduction technique for gate-level timing, SI, power, and variation analysis

Standard cell libraries are used extensively in CMOS digital circuit designs. In the past ten years, standard cell library size has increased by more than 10X. Reducing the library size is becoming a must. In this paper, we present an efficient piece-wise nonlinear library modeling format and library size reduction technique. Instead of using tables and vectors, this format uses base templates (curve or surface templates) to model the shape of curves or surfaces. It works very well for standard cells that exhibit similar behaviors. It is also efficient because the shape can be modeled by a single id. This technique can be applied to timing, SI, power, and variation modeling. It can be directly applied to the traditional nonlinear delay model (NLDM) and the recently developed current source models. This paper also presents a fast method for efficiently selecting the optimal template and detecting bad library data. Our technique uses standardized base templates and allows using any curves or shape functions as base templates. Base templates can be created as needed, and the optimal templates are selected during the model creation process. The fitting and modeling process becomes much simpler and more efficient. It avoids many difficult issues such nonlinear fitting or over-fitting. The modeling accuracy can be easily controlled. Because this format is simpler, using this format could also help speed up the calculation. Several examples are provided in this paper to show this technique is generic, robust, and efficient. Results show .lib library size can be reduced by 5~10X. Experiments using an industry-leading STA tool show the impact on accuracy is ignorable. This technique also help reduces STA tool memory usage and improves runtime.