Title :
Rapid layout synthesis for analog VLSI
Author :
Walczowski, L.T. ; Waller, W.A.J. ; Nalbantis, D. ; Shi, K.
Author_Institution :
Electron. Eng. Labs., Kent Univ., Canterbury, UK
Abstract :
A technology independent synthesis system which rapidly generates the layout of analog VLSI circuits has been developed. Based on a specification of a circuit´s required performance and the target process, a design rule correct layout is generated. The complete system has been tested by synthesizing op amps in the CMOS and bipolar domains. Comparison of the specification with results of simulating the circuit extracted from the synthesized layout, show that the system is accurate to within a few per cent for most parameters
Keywords :
VLSI; analogue integrated circuits; circuit layout CAD; integrated circuit layout; analog VLSI; design rule correct layout; rapid layout synthesis; technology independent synthesis system; CMOS technology; Circuit simulation; Circuit synthesis; Circuit testing; Laboratories; Object oriented modeling; Operational amplifiers; Space exploration; System testing; Very large scale integration;
Conference_Titel :
Electronics, Circuits, and Systems, 1996. ICECS '96., Proceedings of the Third IEEE International Conference on
Conference_Location :
Rodos
Print_ISBN :
0-7803-3650-X
DOI :
10.1109/ICECS.1996.582845
