• DocumentCode
    3093467
  • Title

    Yield evaluation of analog placement with arbitrary capacitor ratio

  • Author

    Chen, Jwu-E ; Luo, Pei-Wen ; Wey, Chin-Long

  • Author_Institution
    Dept. of Electr. Eng., Nat. Central Univ. Jhongli, Taoyuan
  • fYear
    2009
  • fDate
    16-18 March 2009
  • Firstpage
    179
  • Lastpage
    184
  • Abstract
    Capacitance mismatch can be generally attributed two sources of errors: random mismatch and systematic mismatch. Random mismatch is caused by the process variation, while systematic mismatch is mainly due to asymmetrical layout and processing gradients. Common centroid structure may reduce the systematic mismatch, but not the random mismatch. Based on spatial correlation model, this study derives the relationship among correlation, mismatch, and variation of capacitance ratio. Results show that the placement of unit capacitance array with higher correlation results in lower mismatch and lower variation of capacitance ratio. For any arbitrary capacitance ratio, i.e., more than two capacitors, if the summation of correlation coefficients for all capacitance pairs is defined as "index", the placement with higher index results in higher yield, where the yield is defined as the ratio of the acceptable designs over the sample size. In other words, one can find a near-optimal placement which has better yield by using the simple calculation of index, instead of the complicated circuit simulations.
  • Keywords
    analogue circuits; capacitance; capacitors; network analysis; analog placement; capacitance mismatch; capacitance ratio; capacitor; centroid structure; correlation coefficient summation; random mismatch; spatial correlation model; systematic mismatch; yield evaluation; CMOS technology; Capacitance; Capacitors; Circuit simulation; Numerical analysis; Reactive power; Routing; Spatial correlation; Yield Evaluation; capacitance mismatch; process variation; yield analysis;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Quality of Electronic Design, 2009. ISQED 2009. Quality Electronic Design
  • Conference_Location
    San Jose, CA
  • Print_ISBN
    978-1-4244-2952-3
  • Electronic_ISBN
    978-1-4244-2953-0
  • Type

    conf

  • DOI
    10.1109/ISQED.2009.4810290
  • Filename
    4810290