Statistical yield analysis of silicon-on-insulator embedded DRAM

We study the yield of a 65 nm SOI eDRAM design. The impact of random dopant fluctuations in the cell and micro sense amp is studied under different systematic corner and device type considerations. Trench capacitor variation effects and yield timing windows are evaluated. By analyzing the circuit hierarchy, we are able to understand yield trends and hence suitable design guidelines. For the first time a fast Monte Carlo statistical analysis approach is employed for eDRAM analysis. For this, we rely on a well-developed SRAM statistical yield analysis methodology. It is shown that a multiplicity of devices and design considerations can be critical based on the memory operating corners and conditions. It is also shown that high vt sense amp devices, unlike low Vt devices, enable sufficient design yield windows.