Erect of regularity-enhanced layout on printability and circuit performance of standard cells

As the minimum feature size shrinks down far below sub-wavelength, Restricted Design Rule(RDR) or layout regularity plays an important role for maintaining pattern fidelity in photo lithography. However, it also incurs overheads in layout area and circuit performances. Therefore it is important to find an appropriate level of regularity that gives the best trade-or among manufacturability, cost, and performance for each process technology. This paper discusses the erect of layout regularity on printability and circuit performance in 90-45 nm processes by lithography simulation and real chip measurement. It is shown that we can focus more on circuit performance with less on layout regularity in a 90 nm process while adequate amount of regularity is imperative for ensuring proper amount of lithographic process windows in a 45 nm process. We demonstrate the quantitative evaluation of the trade-or between printability and circuit performance of regularity-enhanced standard cells.