DocumentCode
3093572
Title
Private cache partitioning: A method to reduce the off-chip missrate of concurrently executing applications in Chip-Multiprocessors
Author
Hao, Li ; Tao, Liu ; Guanghui, Liu ; Lunguo, Xie
Author_Institution
Dept. of Comput. Sci., Nat. Univ. of Defense Technol., Changsha, China
Volume
4
fYear
2011
fDate
11-13 March 2011
Firstpage
254
Lastpage
259
Abstract
When there are several application running on Chip-Multiprocessors (CMPs), it is a problem to allocate the on-chip cache capacities between these competing applications. Cache partitioning is commonly used to solve this problem. Existing cache partitioning schemes either dedicate to the shared design or partition the last level cache depending on limited memory information. This paper presents Private Cache Partitioning, a low-overhead, runtime mechanism that partitions all of the private low level caches which are organized as a large shared cache by a distributed directory. The experiment results show that PCP reduces the overall missrate of competing applications and improves the throughput as well as the weighted speedup.
Keywords
cache storage; microprocessor chips; PCP; chip-multiprocessors; distributed directory; off-chip missrate reduction; on-chip cache capacities; private cache partitioning scheme; Benchmark testing; Coherence; Hardware; Measurement; Partitioning algorithms; System-on-a-chip; Tiles; Chip-Multiprocessor; DCE; private cache; private cache partitioning;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer Research and Development (ICCRD), 2011 3rd International Conference on
Conference_Location
Shanghai
Print_ISBN
978-1-61284-839-6
Type
conf
DOI
10.1109/ICCRD.2011.5763907
Filename
5763907
Link To Document