Trading off higher execution latency for increased reliability in tile-based massive multi-core architectures

Massive multi-core architectures provide a computation platform with high execution throughput, enabling the efficient execution of workloads with a significant degree of thread-level parallelism, like networking, DSP and e-commerce. The burst-like nature of these workloads render most of the cores idle most of the time. Therefore, there is a large potential for power savings by power gating these idle cores. The ideal scenario from a power dissipation point of view is to execute the requests as fast as possible so that the cores can be power gated the longest. But due to the exponential dependency of (static) power on temperature, it may be the case that a cluster of spatially close cores consumes more than if these cores were farther apart from each other. The former case may certainly be best for performance (since the cores are closer to the neighbor´s caches), but in the presence of spare cores in the die, it may be possible that by executing the requests in distant cores the overall throughput is still maintained and at the same time both power and hot spots are reduced, thus increasing the processor´s reliability. In this work, the power, performance and thermal behavior of a tile-based massive multi-core architecture is modeled and evaluated under different workload scenarios. Under a low ingress rate of requests or low inter-core communication trafic, both higher power savings and more uniformly chip wear are obtained by assigning requests to physically distant cores.