Implementation of a self-timed asynchronous parallel FIR filter using CSCD

This work presents various implementation issues of the self-timed asynchronous parallel finite impulse response (F1R) filter. The main objective was to design all the necessary operational blocks using VHDL and commercial electronic design automation (EDA) tools in order to prove that asynchronous current-sensing completion detection (CSCD) circuits can be designed with traditional EDA tools targeted originally for synchronous designs. In order to make the design steps more effective, some improvements for the EDA software have also been proposed including the graphical control block design in a single design window and the design space exploration method for logic synthesis.