hArtes design flow for heterogeneous platforms

The hArtes -holistic approach to reconfigurable real time embedded systems- design flow addresses the development of an holistic tool-chain for reconfigurable heterogeneous platforms. The entire tool-chain consists of three phases: algorithm exploration and translation, design space exploration and system synthesis. This paper evaluates the tools in the design space exploration phase and the system synthesis phase. The tools in the design space exploration phase facilitate task partitioning, task optimization and assignment of the tasks to the appropriate hardware element. The tools in the system synthesis phase facilitate the hardware/software co-design of embedded applications and perform compilation and HDL generation. The HDL designs are generated with a view of actual hardware/software co-execution on the real hardware platform. The XML architecture description file and the C pragma notations are used for information exchange between different tools. The XML architecture description file is also used to provide a flexible specification of the target architecture. Experimental results with H.264 video encoding application shows the viability of the hArtes design flow.