DocumentCode :
3094010
Title :
Dynamic tree reconstruction with application to timing-constrained congestion-driven global routing
Author :
Yan, Jin-Tai ; Lee, Chia-Fang ; Chen, Yen-Hsiang
Author_Institution :
Dept. of Comput. Sci. & Inf. Eng., Chung Hua Univ., Hsinchu, Taiwan
fYear :
2006
fDate :
3-7 Jan. 2006
Abstract :
In this paper, based on timing-constrained Steiner-point location flexibility in any Y-type wire, a dynamic SA-based timing-constrained flexibility-driven SRT (DSTF_SRT) approach with the congestion weighs is firstly proposed to obtain a better timing-constrained flexibility-driven SRT by reassigning the feasible locations of the Steiner points in a SRT. Furthermore, the concept of dynamic tree reconstruction is applied to timing-constrained congestion-driven global routing. The experimental results show that our proposed TCGR_DTR algorithm can obtain a better timing-constrained congestion-driven global routing result than the HBA+TRR [Hu, 2000] and TCGR [Yan, 2004] algorithm for the tested benchmark circuits.
Keywords :
integrated circuit design; integrated circuit interconnections; network routing; trees (mathematics); TCGR_DTR algorithm; Y-type wire; benchmark circuits; dynamic tree reconstruction; timing-constrained Steiner point location flexibility; timing-constrained congestion-driven global routing; timing-constrained flexibility-driven SRT; Application software; Benchmark testing; Circuit testing; Computer science; Delay; Integrated circuit interconnections; Routing; Steiner trees; Timing; Wire;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Design, 2006. Held jointly with 5th International Conference on Embedded Systems and Design., 19th International Conference on
ISSN :
1063-9667
Print_ISBN :
0-7695-2502-4
Type :
conf
DOI :
10.1109/VLSID.2006.76
Filename :
1581446
Link To Document :
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