DocumentCode
3094037
Title
An efficient reliability evaluation approach for system-level design of embedded systems
Author
Israr, Adeel ; Shoufan, Abdulhadi ; Huss, Sorin A.
Author_Institution
Integrated Circuits & Syst. Lab., Tech. Univ. Darmstadt, Darmstadt, Germany
fYear
2009
fDate
16-18 March 2009
Firstpage
339
Lastpage
344
Abstract
A system-level design process of reliable systems demands efficient reliability evaluation of the explored design alternatives. This paper presents a new approach to accelerate the reliability evaluation and, thus, the design space exploration for reliable systems. A new data structure denoted as system error decision diagram (SEDD) is proposed, which is based on both binary decision diagrams to model permanent errors and zero-suppressed decision diagrams to model transient errors. Both constructing the SEDD diagram and evaluating reliability based on it are detailed in an algorithmic way. The proposed approach is demonstrated for a control system taken from the automotive domain.
Keywords
binary decision diagrams; embedded systems; fault tolerant computing; automotive domain; binary decision diagrams; design space exploration; embedded systems; reliability evaluation approach; system error decision diagram; system-level design; zero-suprressed decision diagrams; Automotive engineering; Binary decision diagrams; Boolean functions; Data structures; Embedded system; Integrated circuit reliability; Process design; Scheduling; Space exploration; System-level design; System Error Decision Diagram; embedded system; permanent error; reliability evaluation; system-level design; transient error;
fLanguage
English
Publisher
ieee
Conference_Titel
Quality of Electronic Design, 2009. ISQED 2009. Quality Electronic Design
Conference_Location
San Jose, CA
Print_ISBN
978-1-4244-2952-3
Electronic_ISBN
978-1-4244-2953-0
Type
conf
DOI
10.1109/ISQED.2009.4810317
Filename
4810317
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