24GHZ dual core PLL design for 60 GHz transceiver and efficient validation methodology

Design and validation of millimeter-wave (MMW) devices is a significant challenge due to the design difficulties in meeting GHz performance constraints and the cost and complexity of test instrumentation needed to validate the circuits. In this paper a 1-V dual-core 24GHz PLL design is presented and it is shown how relatively low cost test instruments utilizing incoherent undersampling can be used to verify the noise performance of a PLL. The 24GHz PLL is implemented to provide more frequency margin and reliability for a 60GHz super-heterodyne transceiver. The incoherent undersampling method is proposed to test different performances of the PLL. Measurement results applying a sampling frequency below 1 GHz are shown for frequency reconstruction and jitter separation.