A SW-HW implementation of arbitration protocols

In this study, we discuss arbitration aspects concerning a segmented bus platform for SOC, and analyze a software implementation of the related procedures. Placed somewhere mid-way between the classical system bus and the network on chip approaches, the segmented bus architecture provides certain performance improvements in comparison with the first, while employing a much simpler communication structure and algorithm than those thought for the second. Our implementation strategy targets an FPGA technology.