A comprehensive solution for true hierarchical timing and crosstalk delay signoff

Leading edge technology advancements have posed big challenges for the digital design flow. Designing multi-million gate ICs at aggressive cycletimes requires new design methodologies and innovative approaches. Hierarchical analysis is a key need to achieve these cycletime goals and gain capacity and runtime advantages in the design flow. Timing and crosstalk delay closure are iterative and hierarchical analysis gains significant cycletime in the overall closure process. In this paper, we present a complete solution for true hierarchical timing and crosstalk delay signoff. The paper discusses challenging problems and caveats with hierarchical signoff and novel solutions to address them. We explore gaps in hierarchical STA and present the first structured solution for hierarchical signoff. The results show 2x-4x cycletime and memory savings using our hierarchical signoff analysis methodology.