Standby power reduction and SRAM cell optimization for 65nm technology

Standby power is one of the most critical issues in low power chip applications. In this paper, we have investigated the effects of body bias and source bias in 65 nm technology through simulations on SRAM standby current (Isb). The simulation results show a 8X reduction in cell Isb at 125degC FF process corner with a 1.0 V NMOS body bias. This has been experimentally verified on a 16 Mb SRAM testchip. Source biasing is shown to be a more effective technique for room temperature leakage reduction (~3X lower Isb@0.4 V bias). Optimizing the SRAM cell is crucial to meet the product performance requirements across corners and a methodology for the same is also described. The 16 Mb testchip was characterized for read disturb, write margin and read current margin at process corners by applying forward and reverse body biases to shift the cell transistor parameters. Different test sequences tailored for the parameter being measured were used to determine the failing bit count in each case. Voltage schmoo plots were generated from the measured data to obtain the Vccmin at each body bias condition. Based on the above, the threshold voltages of the cell transistors for maximum operating margin were derived.